Power saving is an important aspect in PCIe devices and to leverage this, PCIe6.0 has introduced the L0p feature, which is a substate of the L0 LTSSM state intended to save power by disabling lanes. This feature gives the ability to change the link width without going to Recovery and Configuration LTSSM states and without stalling traffic. Complex mechanisms have been introduced into the existing design flow to accommodate the L0p feature, which makes the verification challenging. For more relevant information on L0p introduction, see Unraveling New Introduced PCIe 6.0 L0p
L0p Mechanism in PCIe6.0
Essentially, the ASPM L0p State is a substate of L0 that provides power savings with short entry and exit latency. L0p is supported only in Flit mode for all data rates. To cater the behavior of the L0p functionality stated in PCIe6.0spec, the L0p downsize and L0p upsize mechanisms have been introduced.
L0p downsize is the process involved in reducing the link width to the target link width programmed in the Device Control 3 Register. This is done by disabling the lanes following the downsizing procedure where EIOS are transmitted on the lanes to be de-activated and other lanes to have data-stream active.
L0p upsize is the process involved in increasing the link width to the target link width programmed in the Device Control 3 Register. This is done by re-activating the disabled lanes following the upsizing procedure where EIEOS and upsize TS1/TS2 are transmitted on the lanes that are to be re-activated and other lanes to have data-stream active.
Figure 1: Example of L0p flow in a x16 Link
Impact of L0p Upsize and Downsize on the PIPE Interface
For the L0p flow in terms of the PIPE interface, the MAC is permitted to drive the PowerDown signal on the disabled lanes while downsizing, by going through the PowerDown handshake mechanism as per the PIPE spec. Similarly, while undergoing L0p up-upsize process, the MAC is responsible for driving the appropriate PowerDown value on the lanes to be re-activated. While driving PowerDown on the inactive lanes, the MAC is expected to drive values between 4 – 16, as 1 – 3 are reserved values for P0s, P1 and P2, respectively.
As mentioned in Figure 2 (L0p downsize flow), once the L0p handshake for Downsize is complete, the lanes to be de-activated would transmit the Electrical Idle Ordered Sets (EIOS), followed by the PowerDown handshake where the MAC would drive the PowerDown value on the lanes to be de-activated and handshake from PhyStatus is expected.
Figure 2:L0p Downsize flow (Cadence Implementation)
Similarly, as mentioned in Figure 3 (L0p upsize flow), once the L0p handshake from the DL is competefor Upsize, the MAC would drive the PowerDown value to P0 to re-activate the lanes, and PHY is expected to drive the PhyStatusto acknowledge once its complete. Only then are the EIEOS and upsize TS1/TS2s exchanged.
Figure 3: L0p Upsize flow (Cadence Implementation)
Verification Challenges of L0p on the PIPE Interface
With a complex mechanism of L0p flow introduced in PCIe6.0, verfication faces some major challenges. As this L0p process deals with changing the linkWidth without taking the link into Recovery and Configuration LTSSM states, it involves a great deal of precision while de-activating or re-activating the lanes.
When linkwidth downsizing, the the device needs to transmit EIOS on only the lanes to be de-activated and the other active lanes would transmit Skip Ordered Sets (SKP OS), and the receiver is expected to latch this and negotiate to the downsized linkwidth.
Similarly, during linkwidth upsizing, the in-active lanes are supposed to send upsizeTS1/TS2 there by re-activating the lanes. This process leverages a chance of skew being added, and the receiver has to perform the de-skew process, align the data, and achieve lock to re-establish the in-active lanes.
Moreover, while undergoing L0p flow for upsizing/downsizing, the MAC device is permitted to adhere to the PowerDown handshake mechanims to be performed on the lanes to be de-activated while downsizing, and similarly, for upsizing, the handshake has to be performed on the lanes to be re-activated.
Devices are also permitted to turn off PCLK on the disabled lanes and turn on the PCLK on the in-active lanes while upsizing.
In summary, PCIe6.0 has introduced the L0p feature as a powersaving mode, where complex mechanisms are introduced to adhere to the L0p upsize/downsize. This induces a significant challenge in the verification aspect of L0p. Cadence PCIe 6.0 VIP solutions are proven to verify the PCIe 6.0 features and provide a seamless usage model to cater to the verification of these complex features.
More Information
- For more info on how Cadence PCIe Verification IP and TripleCheck VIP enable users to confidently verify PCIe 6.0, see our VIP for PCI Express, VIP for Compute Express Link and TripleCheck for PCI Express
- See the PCI-SIG website for more details on PCIe in general and the different PCI standards.