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If Only Carl Friedrich Gauss had IntelliGen in 1850
The N-queens issue is a challenging but standard puzzle when it comes to the world of constraint solving. It's a generalization of the 8-queens puzzle, whose description can be found in detail in...
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What Does SystemC Mean for Design and Verification?
My colleague Jack Erickson recently published in the Cadence System Design and Verification Community a blog post entitled "IP Cannot Be an Efficient Abstraction Level without SystemC!" When I saw the...
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Can Your Verification Survive “Boot Camp”?
In Silicon Valley there is a popular fitness program called "Boot Camp" where people volunteer to be run through rigorous exercises by a demanding instructor, analogous to what armies around the world...
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Everything New is Old … Everything Old is New
The title of this post is taken from a fairly obscure 1982 record album (yes, vinyl) on which several classic doo-wop groups performed versions of then-current songs. It's achieved a bit of cult status...
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Rumors of SystemVerilog’s Death Have Been Greatly Exaggerated
Our friend and fellow blogger JL Gray recently published a post with the provocative title "UVM and the Death of SystemVerilog." That sure raised some eyebrows here at Cadence and elsewhere, leading to...
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Tech Tip: The “Show Me” Witness Trace Short-Cut for Design Bring-Up
In a prior Team Verify post, Application Engineer Bin Ju talked about several applications of "Assertion Driven Simulation (ADS) in the Wild". In the following tech tip, allow me (Chris Komar, right)...
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ARM/Cadence Video: How ACE Coherency Adds Value and Verification Complexity
The number of licensees for ARM's Cortex-A15 CPU core is growing rapidly, particularly for mobile computing applications. Customers tell us that's because it provides multiprocessor support and...
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Missing Real-World Assertions in Computer-Land
I was reviewing the page view statistics on the Cadence Functional verification blog and noticed that my previous three posts about missing real-world assertions are among the most read. So, in the...
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Technical Tip on How to Use HDL Assertions in e
While assertion callbacks have existed in Specman/e for several years now, several questions on their usage have surfaced recently, so here is a short refresher on their usage.ABV (Assertion Based...
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Amazon’s New Kindles: More Steps Toward the Paperback Computer
While I understand that a new Kindle Fire at $199 MRSP is significantly more than a dime novel, I assert that today's launch of the new Amazon tablets takes us one step closer to the "paperback...
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Free Webinar Thursday 10/13 -- Automating Assertion Generation for...
Everyone can agree that Assertion-Based Verification (ABV) is a powerful methodology for uncovering corner-case bugs, exposing functional coverage holes, and increasing verification observability....
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Automating UVM to Tackle Insidious HW/SW Bugs
You've just sat through a 2-hour program review. The 30 minutes you spent describing your sparkling new UVM verification environment were electrifying. Of course, the hardware and software reviews...
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Formal Verification with Asynchronous Clocks
Many designs have multiple independent clock inputs with different frequency specifications and/or different frequency ranges. In simulation based environments we see regressions run with randomly...
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Too Many Missing Real-World Assertions?
Well, here I am embarking on my fifth post in which I point out illogical situations I'm come across in my daily life and suggest that the real world is missing some useful assertions. What started out...
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Come See How to Connect SystemVerilog and SystemC Using UVM
All pun-tastic references aside, connecting SystemVerilog and SystemC is becoming a commonplace request. In most cases, the request is to do this using UVM as the testbench methodology. One of our...
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Report: Formal Analysis Papers at CDNLive India 2011
On October 19, 2011 in Bangalore, India more than 800 engineers across all domains came together for CDNLive India 2011. Among the attendees were over 300 design and verification professionals who...
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Verification and the Need for Collaboration
Earlier this week I was at the ARM TechCon in Santa Clara, a show that gets better and busier every year. I was walking around the expo floor, checking out the new vendors and saying hello to old...
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Shameless Promotion: Free Club Formal San Jose, Formal Scoreboard Webinar
Please join Team Verify and other D&V engineers for one or both of the following free events over the next 2 weeks:* This coming Tuesday November 8 starting at 11:30am on our San Jose campus, we...
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Report on CDNLive! India 2011: Provocative Keynotes, Detailed Papers, and...
Recently I had the honor of presenting the functional verification roadmap at CDNLive! India in Bangalore. With the high quality of content and networking, it was easy to see why attendance has...
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Event Report: Club Formal Shanghai
The first "Club Formal" event in China was held in Shanghai on Oct. 21 2011, and as you can see in the image gallery below 24 customers from different 6 companies came together to share their general...
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