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Training Insights - Clean RTL Faster Without Simulation! Here’s How.
RTL designers are challenged by increasingly complex designs. They’re also expected to deliver higher quality RTL to verification teams under tight schedules. And teams want to expose bugs as soon as...
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HyperRam as DRAM for Some Applications!!!
Applications like Automotive, Industrial control panels, Smart Home, Smart watches, smart speakers and bends require Low cost, Low power consumption, High computing efficiency, Easy to control and Low...
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DisplayPort 128b/132b Concurrent LTTPR Link Training
Before a video frame can be sent, the Source (DP-TX) must complete link training (LT) with the downstream devices. DisplayPort (DP) version 2.0 specification mandates support for a 128b/132b link layer...
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Taking LPDDR5 to the Next Level
To cater to ever-increasing bandwidth demands from low-power DRAMs especially for devices like cell phones, tablets and others with limited power budgets, JEDEC has extended the clock frequencies...
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Webinar: Using e Reflection
Join Cadence Training and Software Architect Efrat Shneydor for this free technical Training Webinar.Reflection is a unique capability in the e language, providing a deep inspection of the program,...
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Training Insights - Clean RTL Faster Without Simulation! Here’s How.
RTL designers are challenged by increasingly complex designs. They’re also expected to deliver higher quality RTL to verification teams under tight schedules. And teams want to expose bugs as soon as...
View ArticleClik here to view.
HyperRam as DRAM for Some Applications!!!
Applications like Automotive, Industrial control panels, Smart Home, Smart watches, smart speakers and bends require Low cost, Low power consumption, High computing efficiency, Easy to control and Low...
View ArticleClik here to view.
DisplayPort 128b/132b Concurrent LTTPR Link Training
Before a video frame can be sent, the Source (DP-TX) must complete link training (LT) with the downstream devices. DisplayPort (DP) version 2.0 specification mandates support for a 128b/132b link layer...
View ArticleClik here to view.
Taking LPDDR5 to the Next Level
To cater to ever-increasing bandwidth demands from low-power DRAMs especially for devices like cell phones, tablets and others with limited power budgets, JEDEC has extended the clock frequencies...
View ArticleClik here to view.
Webinar: Extend the Language Using Specman e Macros!
Using Cadence® Specman® Elite macros lets you extend the e language ─ i.e. invent your own syntax.Today, every verification environment contains multiple macros. Some are simple “syntax sugaring” and...
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Training Insights — Metastability-Aware Verification: Elevate Your Signoff...
I hope you enjoyed and got good insights about the Cadence® JasperGold® CDC during the previous CDC webinar "Still Relying on Static-Only CDC Signoff? Introducing the JasperGold CDC App". If you didn't...
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PIPE SerDes Architecture for PCIe Gen 5 and Beyond
Intel PIPE (PHY Interface for PCIE, SATA, USB3.1, DisplayPort and USB4) specification has been ubiquitous PHY interface for accelerating the design and verification of higher layer protocol stacks for...
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Why IDE Security Technology for PCIe and CXL?
The new cloud, AI, Analytics, and Edge usage models with exponential data growth and connection drive the evolution of high-bandwidth PCIe (Peripheral Component Interconnect Express) version 5.0 and...
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Comprehensive Approach to Verification of Interconnect-Centric Systems
Many of today’s SoCs are built around multi-layered, sophisticated interconnect IP components that link together multiple processor cores, caches, memories, and dozens of other IP blocks. These...
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Training Insights - Addressing Security Verification Requirements with...
As a chip designer, you’re probably spending as much headspace on security threats as you are on traditional challenges like power, speed, and functionality. Recent microarchitectural vulnerabilities...
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Verification of Integrity and Data Encryption(IDE) for PCIe Devices
The concept of Trusted Execution Environments (TEE) was developed in the early 2000s to standardize key encryptions, end-to-end security and authenticity, and confidentiality of devices in a system....
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Single DRAM or Multi-DRAMs Memory Sub-system for Your Next SOC ?
Even with the DRAM capacity going up with each generation of DRAM, the demand for memory densities by variety of applications, is growing at even faster rate. To support these high memory densities...
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Why is Ethernet Time-sensitive Networking (TSN) Adaptation So Rapid in the...
At a particular point in time, the automotive industry continued to add more and more sensors and electronic control units to vehicles. All these sensors and actuators used to connect through CAN and...
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From AMBA ACE to CHI, Why Move for Coherency?
Introduced back in 2011, ACE (AXI Coherency Extensions) grew from existing AXI protocol, to satisfy the cache coherency maintenance demands of SOCs with multi core processors and shared caches in smart...
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5G Network Revolution for Enhanced User Experience and Industry Digitalization
The emerging 5G network is the 5th generation of the cellular network. A 5G network allows handling a thousand times more traffic than today's networks. Not only is it faster than the 4G network, but...
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