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Improving Tests Efficiency Using Coverage Callback
When you go to the store, you walk until you get there, stop, get your groceries, and go back home. You do not start circling around the block for few rounds. You do not say “if I walk around the block...
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Training Insights - Comprehensive RTL Signoff Using JasperGold Superlint App
Most have heard the phrase "time is money". Thinking more about it, probably the right phrase would be "time is more valuable than money". People look at their bank accounts with great attention but...
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Improving Tests Efficiency Using Coverage Callback (part 2)
In recent blogs - specman-callback-coverage-api and improving-tests-efficiency-using-coverage-callback - we shared some ideas about how to employ the new Coverage Callback API for increasing the tests...
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Troubleshooting Xcelium Errors/Warnings with xmhelp/xmbrowse and Cadence...
I joined Cadence in July 2000 and was immediately put on a three-month training to learn and understand the simulator tools. There were formal training sessions, and I had a mentor whom I could ask all...
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Higher FLASH Throughput for Your Next SoC Design
Memory is an important part of every electronic system, still it is increasingly becoming a performance bottleneck. While NAND flash is primarily important in consumer and computing applications, there...
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Training Insights - Clean RTL Faster Without Simulation! Here’s How.
RTL designers are challenged by increasingly complex designs. They’re also expected to deliver higher quality RTL to verification teams under tight schedules. And teams want to expose bugs as soon as...
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HyperRam as DRAM for Some Applications!!!
Applications like Automotive, Industrial control panels, Smart Home, Smart watches, smart speakers and bends require Low cost, Low power consumption, High computing efficiency, Easy to control and Low...
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DisplayPort 128b/132b Concurrent LTTPR Link Training
Before a video frame can be sent, the Source (DP-TX) must complete link training (LT) with the downstream devices. DisplayPort (DP) version 2.0 specification mandates support for a 128b/132b link layer...
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Taking LPDDR5 to the Next Level
To cater to ever-increasing bandwidth demands from low-power DRAMs especially for devices like cell phones, tablets and others with limited power budgets, JEDEC has extended the clock frequencies...
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Webinar: Extend the Language Using Specman e Macros!
Using Cadence® Specman® Elite macros lets you extend the e language ─ i.e. invent your own syntax.Today, every verification environment contains multiple macros. Some are simple “syntax sugaring” and...
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Transport Layer – The Backbone of a USB4 Router
It won’t be in-correct to say that transport layer of a USB4 router is the backbone of it. It is a layer that holds all the various other layers together. It provides the very essential services like...
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Verifying Protocol Tunneling with Cadence USB4 VIP — The Multiprotocol Advantage
All the workings of USB4 protocol are primarily about how to transfer the native protocol data through tunneling from their originating points to respective destinations. One may verify thoroughly the...
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TileLink: Chip-Scale Cache-Coherent Interconnect Protocol
RISC-V, an open specification of an Instruction Set Architecture (ISA), which was designed to be scalable for a wide variety of applications has been enjoying wide-spread adoption in the...
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CCIX Coherency: Verification Challenges and Approaches
Cache coherency is not a new concept. Coherent architectures have existed for many generations of CPU and Interconnect designs. Verifying adherence to coherency rules in SoCs has always been one of the...
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What Is New in the Latest AMBA 5 ACE, AXI and AHB Protocol Specification...
The industry-standard ARM AMBA® 5 protocol specifications continue to evolve, further improving performance and efficiency of key ARM architecture features. Besides the updates of powerful AMBA CHI...
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What Disruptive Changes to Expect from PCI Express Gen 6.0
PCIe (Peripheral Component Interconnect Express) has long been the backbone of complex systems, and provides a high-bandwidth, high-performance link for interconnecting devices imposed by cloud-based...
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Introduction to Macros – Answers to Your Questions
Thanks to all the people who attended the webinar Extend the Language! An Introduction to Specman Macros that we had on March the 17th. If you did not attend, or attended and want to see it again – you...
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How to Verify LPDDR5 from IP to System Level?
LPDDR5 DRAM aims to serve a wide array of markets, including automotive, client PCs and networking systems built for 5G and AI Application. So not only that the JEDEC LPDDR5 specification has seriously...
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AMBA 5 ACE/AXI Specification Updates and Their Support in Cadence ACE/AXI VIP
As discussed in the previous blog, the AMBA® 5 specification updates introduced several performance improvement features which align the AMBA5 ACE/AXI protocol with AMBA® 5 CHI (Coherent Hub Interface)...
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Higher FLASH Throughput for Your Next SoC Design
Memory is an important part of every electronic system, still it is increasingly becoming a performance bottleneck. While NAND flash is primarily important in consumer and computing applications, there...
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