The FPGA market is rapidly growing in the traditional Aero-Defense sector as well as in the emerging sectors like Automotive and IoT. FPGA design is considered relatively simple compared to the complexities posed by an SoC design, but FPGA verification is not that simple. Traditionally, companies have been using FPGA vendor tools, methodologies, and flows for verification, but this is proving to be insufficient due to the challenging requirements of quality and robustness. It is also inefficient, due to the slow simulation speed for large regression test suites. The quality and robustness thus cannot be compromised for mission-critical designs in Aero-Defense and Automotive spaces. Moreover, verification becomes challenging for FPGA to ASIC design flows due to increased complexity.
StreamDSP, a digital design company specializing in video processing and high-speed serial communications cores for FPGAs and ASICs, faced similar verification challenges for their FPGA-based designs for defense applications. In this blog, we will delve into the typical FPGA verification challenges and how StreamDSP was able to overcome them by easily migrating to Cadence Xcelium and thereby achieving 3X to 4X performance over other major simulators.
Complexity of StreamDSP FPGA Designs
StreamDSP’s VITA 17.1 and VITA 17.3 IP cores support low latency, highly scalable streaming data interconnect for remote sensor applications such as radar and signal collection. These IP blocks have seen wide adoption across major defense contractors. The VITA 17.3 protocol supports next-generation features such as 64B/67B encoding, far-end return status, and multi-lane channel bonding to create flexible and scalable high-bandwidth links with a common user interface across all technologies. 
FPGA Verification Challenges
Verification of the FPGA-based high-speed serial communication IP is complex, and a large number of tests are run to meet the stringent quality standards for defense applications. StreamDSP is committed to support every transceiver-based device family from all major FPGA vendors. It gives customers absolute freedom in hardware choice but increases the verification effort and time multifold. Every IP needs to be verified for 30 different FPGA device families. StreamDSP’s expanding IP portfolio and the verification challenges described above were pressing the need for a more efficient verification flow to catch bugs much early. Moreover, StreamDSP was entering into the ASIC market and was looking for comprehensive and efficient verification flows for both FPGA and ASIC. Simulating transceiver models can be very slow, and the simulator performance was proving to be one of the biggest bottlenecks for efficiently running a large number of testcases on diverse FPGA device families.
Cadence Verification Flow and Migration
StreamDSP adopted Cadence verification flow including JasperGold for lint and CDC/RDC, Xcelium for simulation, and SimVision for debugging. JasperGold was pretty easy to set up and use. While StreamDSP was manually finding all the clock crossing paths earlier, JasperGold transformed it to just a push-button flow.
StreamDSP focused on the simulator performance as well as the effort and time required for migration. But to their surprise, migration to Xcelium was effortless and quick. It only required changing just a few scripts and that too was made very easy with excellent support from the Cadence team. For each diverse FPGA device family, migration took only 15 minutes and they were ready for verification and performance benchmarking.
Xcelium Performance
Xcelium provided 3X to 4X better run time performance as compared to the other major simulators. StreamDSP used the Xcelium Parallel and Incremental Build flow also for faster compiling and re- compiling. Only a certain part of the code is generally changed after debugging and corresponding fixes in the code. Incrementally re-compiling only the changed files was quite faster and shortened the debug and development cycle. Best-in-class performance in both build and run-time provided a significant gain in the simulation regression throughput.
The 3X to 4X throughput and high quality offered by Xcelium helped StreamDSP to achieve faster yet robust verification closure of IP for diverse FPGA families and ASIC flow. The improved time to market and quality further strengthened the leadership position of StreamDSP in FPGA and ASIC based high-speed serial communication cores for the defense sector. If you are sailing on the same boat, looking for a more efficient and high-quality verification flow, Cadence verification flow will help you to reach your destination faster and safer.
The success story of StreamDSP was presented in the CadenceCONNECT: Mission Critical – A Digital Experience. If you missed attending the virtual live event, watch the on-demand recordings now. For more information, check out the Xcelium page. Stay tuned for the upcoming blogs revealing how Xcelium is being used by industry leaders to improve regression throughput significantly.
-Ankur Jain.