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Xcelium's New Save and Restart Saves You Time
You may have heard about the overhaul to the old save/restart mechanism that was in Incisive—but are you aware of what the new Xcelium Simulator version can do?While the old version is still supported,...
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Leading the Charge: Cadence Announces New Verification IP for UFS 3.0,...
Today, Cadence announced three new VIPs, two of which are industry-firsts! Cadence revealed the first available VIP for CoaXPress for high-speed imaging and the first available VIP for HyperRAM...
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Empowering Generation - Range Generated Fields (RGF)
Specman constraints solver process consists of a series of reductionsand assignments. It reducesthe range of the field value based on the constraints, and then assignsto it a random value from the...
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App Note Spotlight: Streamline Your SystemVerilog Code, Part II -...
Welcome back to a special multi-part edition of the App Note Spotlight, where we’ll continue highlighting an interesting app note that you may have overlooked—Simulation Performance Coding Guidelines...
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RAK Attack: Verifying Power Intent for Low Power Mixed Signal SoCs
The wait is finally over—the Rapid Adoption Kit (RAK) for verifying the power intent of low-power mixed signal SoCs is here! The RAK is a tutorial designed to clearly show, through example, how to...
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Come Join Us for "Deep Dive into the UVM Register Layer" - A Webinar From Duolos
Join us on September 14th for a free one-hour webinar on the finer aspects of the UVM register layer. We’ll be focusing on key aspects of the UVM Register Layer that can help you with your UVM modeling...
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App Note Spotlight: Streamline Your SystemVerilog Code, Part IV - Dynamic...
Welcome back to the fourth installment of a special multi-part edition of the App Note Spotlight, where we’ll continue highlighting an interesting app note that you may have overlooked—Simulation...
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Specman 18.09: Avoiding the Small Annoying Mistakes
Specman 18.09: Avoiding the small annoying mistakes In almost every industry, one has the potential of making a small mistake that may cost hours or days to find. The following interesting article...
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Improving Your Testbench Flexibility with Enhanced Specman Templates
Cadence® Specman® Elite delivers faster and higher quality verification at block, chip, and system levels. The tool is cloud ready, supports industry-standard verification languages, and is compatible...
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Speedup SystemVerilog UVM Debug Regression Time with Dynamic Test Load
Microsemi has been evaluating a unique feature in Xcelium System Verilog UVM Dynamic Test Load for some time now, and they shared their thoughts on it in a paper presented at CDNLive San Jose April...
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DMS 2.0 - What's Cool and What's New
Are you aware of all the cool new features in Digital Mixed Signal 2.0 (DMS 2.0)? Provided with the Xcelium Parallel Simulator versions 17.10 and beyond, DMS 2.0 brings you all kinds of new and...
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Is it Time to Verify Your Chips in the Cloud? Part 1 of 3
Welcome to the first installment of a three-part blog series examining the issues and opportunities for performing verification in the cloud.For a while now, there’s been a growing interest in...
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App Note Spotlight: Streamline Your SystemVerilog Code, Part III -...
Welcome back to the third installment of a special multi-part edition of the App Note Spotlight, where we’ll continue highlighting an interesting app note that you may have overlooked—Simulation...
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Is It Time to Verify Your Chips in the Cloud? Part 2 of 3
Welcome back to our series on cloud verification solutions. This is part two of a three-part blog—you can read part one here.The high-performance computing (HPC) market continues to grow. Analysts say...
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Learn How Valens uses Specman Macros Automate Configuration of Verification...
Valens has achieved success through applying Specman to their verification projects. At DVCon EMEA (Oct 24-25) you can learn how their use of Specman Macros to automate configuration of the...
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Cadence Announces Full Cadence Verification Suite Compatibility for Arm-Based...
On October 16, 2018, Cadence Design Systems, Inc announced that, through a wide-reaching system design enablement collaboration, the Cadence Verification Suite is ready for use on Arm®-based...
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Is it Time to Verify Your Chips in the Cloud? Part 1 of 3
Welcome to the first installment of a three-part blog series examining the issues and opportunities for performing verification in the cloud.For a while now, there’s been a growing interest in...
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App Note Spotlight: Streamline Your SystemVerilog Code, Part III -...
Welcome back to the third installment of a special multi-part edition of the App Note Spotlight, where we’ll continue highlighting an interesting app note that you may have overlooked—Simulation...
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Is It Time to Verify Your Chips in the Cloud? Part 2 of 3
Welcome back to our series on cloud verification solutions. This is part two of a three-part blog—you can read part one here.The high-performance computing (HPC) market continues to grow. Analysts say...
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UVM-ML- Managers’ Freedom of Choice
Freedom of choice is a term we hear a lot, especially in the last 10 years. It is defined in wikipedia as “an individual's opportunity and autonomy to perform an action selected from at least two...
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